Fusible links (e.g. nichrome, doped polysilicon strips) are commonly employed in memories, logic circuit arrays, amplifier circuits, etc. to define at least one prescribed circuit or subsystem state or functionality. In memory logic devices an individual logic element (e.g. a one-bit memory cell) is typically comprised of an input/output switch (an MOS or bipolar transistor or diode) and a fusible (resistive) element coupled together between an address line and an output (bit) line for that cell. The fusible element itself is normally of very low resistance which is converted to a high resistance (open circuit) state by applying a predetermined amount of energy (power .times.time) to the element, so as to sever or "blow" the fuse. The amount of power delivered to the fusible element depends upon several factors including voltage level, the characteristics of a programming switch (transistor) through which the fusible element of a particular fusible element is selected, the characteristics of the memory cell transistor and the resistance of the line through which the memory cell of interest is addressed.
A portion of an exemplary array (M rows.times.N columns) of memory cells, in which fusible elements are employed, is diagrammatically illustrated in FIG. 1 as comprising a (row) address input 11 coupled to a row driver 12, the output of which is supplied to a word line 13 for driving all the memory cells of that particular row. In FIG. 1, only two memory cells 16-1 and 16-N of the row of interest are shown, in order to simplify the drawing. Of these two cells, memory cell 16-1 is physically located closest to row driver 12, while memory cell 16-N is physically located farthest away from row driver 12. Each memory cell contains a transistor switch and a fusible element for selectively controlling the state of an associated bit (column) line.
For this purpose, memory cell 16-1 contains a bipolar transistor 23, the collector 23C of which is coupled to collector voltage supply terminal (+V), the base 23B of which is coupled to row line 13 and the emitter 23E of which is coupled via fusible link 24 to an associated bit line 21-1. Similarly, memory cell 16-N contains a bipolar transistor 25, the collector of which is coupled to collector voltage supply terminal (+V), the base 25B of which is coupled to row line 13 and the emitter 25E of which is coupled via fusible link 26 to an associated bit line 16-N.
For selectively programming the memory cells of the array a respective programming switch is coupled to each bit line 21-1 . . . 21N. Thus bit line 21-1 has a programming MOSFET switch 31-1 the drain of which is coupled to line 21-1 and the source of which is coupled to a reference potential terminal (e.g. ground). The gate of each programming MOSFET is coupled to a respective bit line enable input. To selectively sever or "blow" the fuse of a particular memory cell, respective address/enable signals are applied to the associated row driver 12 and programming switch 31-i for that memory cell, thereby turning-on the bipolar transistor of the memory cell and the MOSFET switch of the programming switch, to provide a "fuse-rupturing" current flow path from +V to ground through the fusible link of the addressed cell.
In memory arrays where the word line 13 is made of metal (e.g. gold or aluminum) there is no appreciable voltage drop from memory cell 16-1 to cell 16-N along line 13, so that each cell may be programmed with the same expectancy of success. However, in memory arrays wherein the resistance of the word line 13 is not insignificant, as in the case of an interconnect configuration using polysilicon as the word line material, the resistance of the line, denoted by distributed resistors 14 in FIG. 1, introduces a significant voltage drop along the line from the memory cell 16-1 closest to driver 12 to the memory cell 16-N farthest away from driver 12. For long word lines, as are found in high density memories, for example, this voltage drop reduces the effective base drive voltage to the bipolar transistors of the respective memory cells, thereby reducing the current flow to the fusible elements, which can affect programming yield and reliability over the life of the array by not sufficiently "blowing" the fusible element to produce the desired high resistance.